High Order FIR Filter Hardware Implementation Complexity Reduction

Abstract

In this paper, the authors propose an algorithm for the hardware implementation complexity reduction of high order FIR-filters. Current algorithm reduces FIR-filters' a number of multipliers expressing initial impulse response samples through the other initial impulse response samples. This approach allows replacing multipliers with shift registers and adders, which leads to reduction of FIR-filters' power consumption and required crystal area. Algorithm works with all types of filters: Low Pass, High Pass, Band Pass, Band Stop and also it supports FIR-filters with symmetrical and asymmetrical impulse responses.