Mohamed El-Badry, M. El-Fiky, Aya Yasser, Ahmed G. Shehata, Mostafa El-Sayeh, A. Sallam, Mostafa Hagras, Ahmed Abdelati, S. Ibrahim
{"title":"A 2.2-pJ/bit 10-Gb/s forwarded-clock serial-link transceiver for IoE applications","authors":"Mohamed El-Badry, M. El-Fiky, Aya Yasser, Ahmed G. Shehata, Mostafa El-Sayeh, A. Sallam, Mostafa Hagras, Ahmed Abdelati, S. Ibrahim","doi":"10.1109/ISSCS.2017.8034899","DOIUrl":null,"url":null,"abstract":"This paper presents a 10-Gb/s power-efficient serial-link transceiver for the Internet-of-Everything applications. The proposed transceiver employs several techniques to reduce the power consumption. This includes the use of forward clocking with a simplified clock recovery scheme, multiplexing the transmitted signal at the output of voltage-mode drivers, and using modified slicers in the receiver side. The proposed transceiver is implemented using a 130-nm CMOS technology. It can transmit and receive 10-Gb/s serial data while employing a 5-GHz forwarded clock. The transceiver consumes 17.5 mA from a 1.2-V supply achieving a power efficiency of 2.2 pJ/bit.","PeriodicalId":338255,"journal":{"name":"2017 International Symposium on Signals, Circuits and Systems (ISSCS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Symposium on Signals, Circuits and Systems (ISSCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCS.2017.8034899","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents a 10-Gb/s power-efficient serial-link transceiver for the Internet-of-Everything applications. The proposed transceiver employs several techniques to reduce the power consumption. This includes the use of forward clocking with a simplified clock recovery scheme, multiplexing the transmitted signal at the output of voltage-mode drivers, and using modified slicers in the receiver side. The proposed transceiver is implemented using a 130-nm CMOS technology. It can transmit and receive 10-Gb/s serial data while employing a 5-GHz forwarded clock. The transceiver consumes 17.5 mA from a 1.2-V supply achieving a power efficiency of 2.2 pJ/bit.