Analysis of 1- bit full adder using different techniques in Cadence 45nm Technology

Abstract

The full adder is an important component for controller or processor design like microprocessors, digital signal processors etc. It is also used to do arithmetic and logical operations. The objective of this project is to reduce power, delay and increase the stability factor of a full adder by using various 1bit full adder designs and techniques. Here 10T full adder circuits using CMOS technology plots the minimum power consumption rather than others. Because CMOS technology dissipates low power. A comparative data analysis is shown for power, delay and stability using SERF (Static Energy Recovery Full Adder), GDI(Gate Diffused Input) method with different number of transistors which is used to extend the battery life. The adders are designed and implemented in the virtuoso platform using Cadence 45nm tool.