Dynamic CMOS Incrementers-cum-Decrementers Based on Least Significant Zero Bit Principle

Abstract

The novel design of a 8-bit decision module that forms the heart of a dynamic CMOS incrementer-cum-decrementer circuit is presented in this work. The new 8-bit decision module is designed on the basis of identifying least significant zero bit (LSZB) in the binary input stream contrary to identification of least significant one bit (LSOB), as is the case with existing approaches, to perform increment-cum-decrement operations. Further, an original cascading architecture has been proposed for building larger size incrementers-cum-decrementers based on the LSZB principle. SPICE simulations reveal that a 32-bit incrementer-cum-decrementer implemented using the proposed LSZB principle dissipates 58.6% less power than its counterpart designs based on the LSOB approach.