A Digital Method for Offset Cancellation of Fully Dynamic Latched Comparators

Abstract

In this paper, we have proposed a two-phase high precision digital offset cancellation method for dynamic latched comparators. The proposed method's first phase is weight balance control, and the second phase is named body bias control. The first phase reduces the offset of the comparator up to a few millivolts, and the second phase alleviates this amount to some decades of microvolts. The main reason for using the second phase is the weight balance calibration's sensitivity to the input pairs sizes and kickback noise. A retiming method is used to control the thermometer code DAC switching activities and minimize the glitches. The thermometer DAC structure is used for the body bias control method instead of R-2R DAC to ensure the body bias controller's monotonic signal. Circuitry simulations are done using Cadence with 180 nm standard CMOS technology under 1 V power supply. A strong-arm dynamic latched comparator is used for our calibration study. Before calibration, the input offset has three times of standard deviation equal to 19.56 millivolts. The weight balance control offset method has reduced this amount to almost 2.8 millivolts. Finally, the fully-calibrated comparator results have an offset equal to 363 microvolts. The calibration clock is set to be 33.3 MHz. Our offset cancellation prepares 53.9 times improvement in the input offset of the comparator using 389 microwatts.