E. Genco, Kyle van Oosterhout, Martijn Timmermans, M. Fattori
{"title":"A High-Gain Low-Noise Transimpedance Amplifier based on Active-Feedback Network","authors":"E. Genco, Kyle van Oosterhout, Martijn Timmermans, M. Fattori","doi":"10.1109/IWASI58316.2023.10164441","DOIUrl":null,"url":null,"abstract":"In this work, we present a novel TIA with ultra-high transimpedance gain, achieved without the use of pseudo-resistors or off-chip resistors. The proposed approach overcomes the conventional trade-offs between noise and gain in the design of a TIA with resistive feedback. The proposed architecture makes use of a transconductor in the TIA negative feedback path to achieve impedance multiplication and enable large transimpedance amplification. Moreover, thanks to the dominant pole positioned at the input of the TIA, circuit stability can be disentangled from the gain when different capacitive loads are connected to the input of the circuit. Simulation results reveal that it is possible to design a TIA with programmable transimpedance gain ranging from 5 M$\\Omega$ (134.1 dB$\\Omega$) to 5 G$\\Omega$(194.4 dB$\\Omega$) and exhibiting a 3dB bandwidth of 1.54 MHz and 23 kHz, respectively when coupled to a current-source with an output capacitance of 20 pF. At the frequency of 20 Hz, the TIA achieves an input referred noise current of 2fA/$\\sqrt{}$Hz and 20 fA/$\\sqrt{}$Hz, for the maximum and minimum gain, respectively. Moreover, the programmable TIA is unconditionally stable by design for any input capacitance equal to or larger than 20 pF. The proposed TIA is implemented in a TSMC 65nm CMOS technology node, it requires an area of 0.045 $\\mu m^{2}$ and consumes 850 $\\mu$W at a power supply of 1.2 V. Thanks to its high-gain, large bandwidth, low-noise performance and its flexibility with the respect to the input source capacitance value, the proposed solution is best suited for the interfacing highly capacitive sensors or as a versatile first stage for the noise performance characterization of solid-state devices.","PeriodicalId":261827,"journal":{"name":"2023 9th International Workshop on Advances in Sensors and Interfaces (IWASI)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 9th International Workshop on Advances in Sensors and Interfaces (IWASI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWASI58316.2023.10164441","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this work, we present a novel TIA with ultra-high transimpedance gain, achieved without the use of pseudo-resistors or off-chip resistors. The proposed approach overcomes the conventional trade-offs between noise and gain in the design of a TIA with resistive feedback. The proposed architecture makes use of a transconductor in the TIA negative feedback path to achieve impedance multiplication and enable large transimpedance amplification. Moreover, thanks to the dominant pole positioned at the input of the TIA, circuit stability can be disentangled from the gain when different capacitive loads are connected to the input of the circuit. Simulation results reveal that it is possible to design a TIA with programmable transimpedance gain ranging from 5 M$\Omega$ (134.1 dB$\Omega$) to 5 G$\Omega$(194.4 dB$\Omega$) and exhibiting a 3dB bandwidth of 1.54 MHz and 23 kHz, respectively when coupled to a current-source with an output capacitance of 20 pF. At the frequency of 20 Hz, the TIA achieves an input referred noise current of 2fA/$\sqrt{}$Hz and 20 fA/$\sqrt{}$Hz, for the maximum and minimum gain, respectively. Moreover, the programmable TIA is unconditionally stable by design for any input capacitance equal to or larger than 20 pF. The proposed TIA is implemented in a TSMC 65nm CMOS technology node, it requires an area of 0.045 $\mu m^{2}$ and consumes 850 $\mu$W at a power supply of 1.2 V. Thanks to its high-gain, large bandwidth, low-noise performance and its flexibility with the respect to the input source capacitance value, the proposed solution is best suited for the interfacing highly capacitive sensors or as a versatile first stage for the noise performance characterization of solid-state devices.