Zhengdong Jiang, Dong Chen, Youxi Zhou, Zhiqing Liu, Chenxi Zhao, K. Kang
{"title":"A 700 MHz-920 MHz CMOS Power Amplifier for LTE Applications","authors":"Zhengdong Jiang, Dong Chen, Youxi Zhou, Zhiqing Liu, Chenxi Zhao, K. Kang","doi":"10.1109/ICMMT.2018.8563705","DOIUrl":null,"url":null,"abstract":"This work presents a CMOS power amplifier (PA) for FDD (band 17, 18, 19 and 20) of 4G cellular applications. In this work, a power cell by using three stacked transistors is proposed. It not only meets the breakdown voltage requirement, but also provides enough power gain and output power. By designing the compact and low-loss layout of the power cell, the power added efficiency (PAE) is increased observably. It is fabricated in 180-nm CMOS with a chip area of $1800 \\ \\mu \\mathrm{m} \\ \\times 1500 \\mu \\mathrm{m}$. The proposed PA achieves a power gain of 37 dB, saturated output power $(\\mathbf{P}_{\\mathbf{s}\\mathbf{a}\\mathbf{t}})$ of 32 dBm, output 1 dB compression point $(\\mathbf{OP}_{\\mathbf{l}\\mathbf{d}\\mathbf{B}})$ of 30.5 dBm and peak PAE of 41.50/0 at 810 MHz.","PeriodicalId":190601,"journal":{"name":"2018 International Conference on Microwave and Millimeter Wave Technology (ICMMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 International Conference on Microwave and Millimeter Wave Technology (ICMMT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMMT.2018.8563705","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This work presents a CMOS power amplifier (PA) for FDD (band 17, 18, 19 and 20) of 4G cellular applications. In this work, a power cell by using three stacked transistors is proposed. It not only meets the breakdown voltage requirement, but also provides enough power gain and output power. By designing the compact and low-loss layout of the power cell, the power added efficiency (PAE) is increased observably. It is fabricated in 180-nm CMOS with a chip area of $1800 \ \mu \mathrm{m} \ \times 1500 \mu \mathrm{m}$. The proposed PA achieves a power gain of 37 dB, saturated output power $(\mathbf{P}_{\mathbf{s}\mathbf{a}\mathbf{t}})$ of 32 dBm, output 1 dB compression point $(\mathbf{OP}_{\mathbf{l}\mathbf{d}\mathbf{B}})$ of 30.5 dBm and peak PAE of 41.50/0 at 810 MHz.