A low voltage low power four quadrant analog multiplier using submicron technology

Abstract

This paper presents a new four quadrant voltage mode analog multiplier using square rooting circuit. The proposed circuit can work for low voltage and low power applications as it uses flipped voltage follower cell. The circuit is designed using 0.18μm CMOS technology and its simulations have been carried out using Cadence Virtuoso environment. The circuit is operated under the supply voltage of 1V and the differential input signals peak to peak voltages of 40mV. The worst case power consumption has been measured from the simulation results as 14μW. Moreover −3dB bandwidth of the circuit has been found to be 530MHz. the operation of the multiplier as a frequency doubler is also verified.