Superscalar SIMD architecture

Abstract

Presents a parallel computer architecture which synthesizes the notions of instruction level parallelism and data parallelism. Extending the work of Siegel and others on reconfigurable SIMD/MIMD architecture, it attains most of the advantages of those machines, via selective execution of a superscalar instruction stream, while retaining most of the cost advantage of the SIMD architectural style. Furthermore, it preserves the single instruction stream framework which makes SIMD machines simpler to program. Finally, it admits the use of compiler techniques to schedule the superscalar instruction stream, allowing the automatic utilization of the latent instruction level parallelism.<>