{"title":"Queuing Theory-Guided Performance Evaluation for a Reconfigurable High-Speed Device Interconnected Bus","authors":"Weiwen Chen, Keni Qiu, Jiqin Zhou, Yuanhui Ni, Yuanchao Xu","doi":"10.1109/Trustcom/BigDataSE/ICESS.2017.320","DOIUrl":null,"url":null,"abstract":"UM-BUS, a reconfigurable high-speed device- interconnected bus, also characteristic of dynamic fault-tolerance and remote access has been proposed to enablelightweight sensor system design in IoTs. Performanceprediction is a key step to build an idea of the worst or best casesbefore real-world deployment of UM-BUS-based systems. Thispaper proposes a queuing theory-guided analytic model whichallows us to obtain an approximation for the average packetdelay as well as exact upper and lower bounds. A set ofexperiments based on MATLAB simulation are conducted to doperformance evaluation. Finally design insights are given forpragmatic implementation.","PeriodicalId":170253,"journal":{"name":"2017 IEEE Trustcom/BigDataSE/ICESS","volume":"379 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE Trustcom/BigDataSE/ICESS","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/Trustcom/BigDataSE/ICESS.2017.320","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract
UM-BUS, a reconfigurable high-speed device- interconnected bus, also characteristic of dynamic fault-tolerance and remote access has been proposed to enablelightweight sensor system design in IoTs. Performanceprediction is a key step to build an idea of the worst or best casesbefore real-world deployment of UM-BUS-based systems. Thispaper proposes a queuing theory-guided analytic model whichallows us to obtain an approximation for the average packetdelay as well as exact upper and lower bounds. A set ofexperiments based on MATLAB simulation are conducted to doperformance evaluation. Finally design insights are given forpragmatic implementation.
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