{"title":"A Time-Based Analogue-to-Digital Converter for ECG Applications","authors":"Atiyeh Karimlou, M. Yavari","doi":"10.1109/ICEE52715.2021.9544304","DOIUrl":null,"url":null,"abstract":"This paper presents a low-power time-based analog-to-digital converter (ADC) for wearable electrocardiogram (ECG) sensor applications. In this work, by applying the difference between two consecutive samples to the input of the conventional voltage-to-time converter, the requirements on the high-frequency ramp signal will be relaxed and we can design for low power consuming implementation. The proposed approach reduces the converter complexity and generates a 1-bit data stream which leads to more power saving. The proposed circuit was designed and simulated in the 180 nm CM OS technology process, achieving a resolution of 10.4 bit and consumes 163 nW power with a supply voltage of 0.8 V.","PeriodicalId":254932,"journal":{"name":"2021 29th Iranian Conference on Electrical Engineering (ICEE)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 29th Iranian Conference on Electrical Engineering (ICEE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEE52715.2021.9544304","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents a low-power time-based analog-to-digital converter (ADC) for wearable electrocardiogram (ECG) sensor applications. In this work, by applying the difference between two consecutive samples to the input of the conventional voltage-to-time converter, the requirements on the high-frequency ramp signal will be relaxed and we can design for low power consuming implementation. The proposed approach reduces the converter complexity and generates a 1-bit data stream which leads to more power saving. The proposed circuit was designed and simulated in the 180 nm CM OS technology process, achieving a resolution of 10.4 bit and consumes 163 nW power with a supply voltage of 0.8 V.