An FPGA Library Based Design of Variable CNN Weight Compression using Resizable K-Means Clustering

Abstract

Convolutional Neural Networks (CNN) is a popular tool used for image recognition. In CNN architecture, a set of weights undergo a series of updating while the training process for image recognition is ongoing. These weight values can be quite a lot in memory consumption. One way to reduce memory consumption is to use a form of weight compression through weight sharing. To do this, one can quantize the weights using K-Means clustering. To use the K means Clustering algorithm, one can manually try different values of K and then choose the best value that can save the CNN memory usage and at the same time will not deteriorate the recognition ability of the CNN. The method of trying different values of K to search for the best compression rate, can be time consuming for the user. In this paper, using XILINX Virtex FPGA library, a proposed hardware model design for a CNN integrated to a resizable Kmeans Clustering Model is presented. The hardware model design highlights the elimination of the manual search for best value of K. A synthesizable hardware model for the control and data path of the integration is proposed. A Hardware Model algorithm for an automated search for the best value of K in steps of 10, is presented. The proposed integration will allow the system to work by itself, to auto search for the best compression ratio after the CNN has finished training.