Multi-core parallel simulation of System-level Description Languages

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI:10.1109/ASPDAC.2011.5722205

R. Dömer, Weiwei Chen, Xu Han, A. Gerstlauer

引用次数: 27

Abstract

The validation of transaction level models described in System-level Description Languages (SLDLs) often relies on extensive simulation. However, traditional Discrete Event (DE) simulation of SLDLs is cooperative and cannot utilize the available parallelism in modern multi-core CPU hosts. In this work, we study the SLDL execution semantics of concurrent threads and present a multi-core parallel simulation approach which automatically protects communication between concurrent threads so that parallel simulation on multi-core hosts becomes possible. We demonstrate significant speed-up in simulation time of several system models, including a H.264 video decoder and a JPEG encoder.

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系统级描述语言的多核并行仿真

系统级描述语言(sldl)中描述的事务级模型的验证通常依赖于广泛的仿真。然而，传统的离散事件(DE)模拟是协同的，不能充分利用现代多核CPU主机的并行性。在这项工作中，我们研究了并发线程的SLDL执行语义，并提出了一种多核并行仿真方法，该方法可以自动保护并发线程之间的通信，从而使多核主机上的并行仿真成为可能。我们演示了几种系统模型在仿真时间上的显著加速，包括H.264视频解码器和JPEG编码器。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

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