Asynchronous parallel genetic algorithm for congestion-driven placement technique

Abstract

Deep-sub-micron technology (DSM) of 0.18 micron and below enable the integration of logical circuits having more than 10 million gates. In such a DSM technology, layout design has become the most important design phase. This paper discusses a novel congestion-driven placement technique based on asynchronous parallel genetic algorithm. The proposed algorithm has a two-level hierarchical structure. For selection control, new objective functions are introduced for wire congestion and chip area. Moreover, the two kind of parallel processing suitable for hierarchical processing is introduced for reduction of run time. Experimental results show improvement comparison with conventional layout technique.