Designing A Compact Convolutional Neural Network Processor on Embedded FPGAs

Abstract

FPGA-based Convolutional Neural Network (CNN) processor has been widely applied for highly-parallelized computations and fast deployment. However, designing on embedded FPGA needs to consider multiple aspects, such as the feasibility of limited configurable resource on FPGA, external memory latency and the scheduling between memory and computation units. These considerations hence hinder the usage of FPGA. Addressing these issues, we elaborate a systematic design approach that allow fast deployment, which includes the parameterized computation and memory unit, which can be configured based on the target platform, and an evaluation approach for searching the optimal setting sets. To evaluate the proposed approach, we performed object detection task, YOLOv2, on PYNQ-Zl and achieved 48.23 GOPs throughputs as well as 0.611 seconds execution time. This is 42.38 and 12.8 times faster than the same inference on CPU and GPU and is 2.36 times faster than other FPGA implementations. Additionally, our created evaluation model is only 5-22% apart from the implementation result, which is 60% less than previous work.