{"title":"Fully integrated active CMOS vector modulator for 802.11a compliant diversity transceivers","authors":"N. Joram, U. Mayer, R. Eickhoff, F. Ellinger","doi":"10.1109/COMCAS.2009.5386002","DOIUrl":null,"url":null,"abstract":"In this paper, a CMOS vector modulator designed for smart antenna arrays at 5.5 GHz is presented. A quadrature all pass filter and sign select switches yield two orthogonal signal paths. Two variable gain amplifiers with strongly reduced phase shift of only ±6 ° are used to weight these paths. It has a phase control range of 360 ° and a gain range of −20 dB to 2.8 dB. The input-referred IP3 is −7 dBm at maximum gain. The current drawn from a 1.5 V supply amounts 12 mA. Using a 180 nm technology, the chip core area amounts 1.2×0.8 mm².","PeriodicalId":372928,"journal":{"name":"2009 IEEE International Conference on Microwaves, Communications, Antennas and Electronics Systems","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE International Conference on Microwaves, Communications, Antennas and Electronics Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/COMCAS.2009.5386002","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 16
Abstract
In this paper, a CMOS vector modulator designed for smart antenna arrays at 5.5 GHz is presented. A quadrature all pass filter and sign select switches yield two orthogonal signal paths. Two variable gain amplifiers with strongly reduced phase shift of only ±6 ° are used to weight these paths. It has a phase control range of 360 ° and a gain range of −20 dB to 2.8 dB. The input-referred IP3 is −7 dBm at maximum gain. The current drawn from a 1.5 V supply amounts 12 mA. Using a 180 nm technology, the chip core area amounts 1.2×0.8 mm².
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