Graph colouring based multi pin net detailed routing for FPGA using SAT

Abstract

A SAT based detailed routing technique for island style FPGA architecture is presented in this paper. This technique uses the graph-colouring paradigm to propose a routing technique which routes multiple nets without decomposing them into 2-pin subnets for simplicity. In spite of this fact, the technique proposed proves to be efficient and scalable since it leverages the computing power of fast SAT solvers running in the back end, as shown by the experiments on benchmark circuits.