{"title":"Fine-Grain Pipelined Reconfigurable VLSI Architecture Based on Multiple-Valued Multiplexer Logic","authors":"Katsuhiko Shimabukuro, M. Kameyama","doi":"10.1109/ISMVL.2017.45","DOIUrl":null,"url":null,"abstract":"This paper presents a novel bit-serial fine-grain pipelined reconfigurable VLSI architecture based on multiplexer logic to achieve high utilization of hardware resources and high throughput. A basic cell is constructed by a logic block composed of a 2-data-input multiplexer and a switch box for data transfer between adjacent logic blocks by 8-near neighborhood mesh network. A multiplexer merged with a latch function is effectively employed for efficient fine-grain pipelined operation. A systematic mapping method for pipelined bit-serial operations is proposed using a data flow graph. As an extension of the reconfigurable VLSI based on the binary multiplexer logic, we introduce linear summation in the data transfer between logic blocks. A 4-valued multiplexer directly controlled by the linear sum can be effectively utilized to reduce complexity of the switch box.","PeriodicalId":393724,"journal":{"name":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.2017.45","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
This paper presents a novel bit-serial fine-grain pipelined reconfigurable VLSI architecture based on multiplexer logic to achieve high utilization of hardware resources and high throughput. A basic cell is constructed by a logic block composed of a 2-data-input multiplexer and a switch box for data transfer between adjacent logic blocks by 8-near neighborhood mesh network. A multiplexer merged with a latch function is effectively employed for efficient fine-grain pipelined operation. A systematic mapping method for pipelined bit-serial operations is proposed using a data flow graph. As an extension of the reconfigurable VLSI based on the binary multiplexer logic, we introduce linear summation in the data transfer between logic blocks. A 4-valued multiplexer directly controlled by the linear sum can be effectively utilized to reduce complexity of the switch box.