Designing a D-Flipflop Using Novel Sleep Transistor Technique

Abstract

D-Flipflops are widely used in designing various analogue, digital and mixed signals. Different shift registers, counters and other circuits are designed using D-Flipflop. To increase the battery life time and reduce the power consumption, the voltage given to the circuit have to be decreased in the Standby mode of operation. In this paper different D Flipflops are designed using techniques like 5 transistor D-Flip Flop, Self-voltage level D-Flipflop and modified SVL (Self Voltage Level) D-Flipflop and Novel sleep transistor technique. Comparisons are made between all the designs in terms of power, delay and leakage power. All the designs are designed and simulated with the help of Cadence Virtuoso in 90nm technology. The leakage power observed in Novel Sleep Transistor technique is 93.5% less than that observed in Modified SVL Technique.