A hierarchical parallel placement technique based on genetic algorithm

Abstract

Deep-sub-micron technology (DSM) of 0.18 micron and below enable the integration of logical circuits having more than 10 million gates. In such a DSM technology, layout design has become the dominant design phase. This paper discusses a novel performance-driven placement technique. The proposed algorithm based on genetic algorithms (GA) has a two-level hierarchical structure. For selection control, new objective functions are introduced for improving chip area, interconnect delay and power consumption. In order to reduce run time, the two kind of parallel processing suitable for hierarchical processing is introduced. Experimental results show improvement comparison with commercial EDA tool.