G. C. Patil, Vijaysinh H. Bonge, M. Malode, Rahul G. Jain
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引用次数: 1
Abstract
In this paper, a novel device structure named as partially insulated (Pi-OX) junctionless transistor (JLT) is proposed and the simulated results below 20 nm have been compared with existing silicon-on-insulator (SOI) JLT. Further, drain-induced barrier lowering (DIBL), subthreshold swing (SS), on-state drive current (ION), off-state leakage current (IOFF), ION/IOFF ratio and static power dissipation (PSTAT) of the proposed Pi-OXJLT and SOIJLT has also been compared. It has been found that, IOFF, DIBL and SS in the case of proposed Pi-OXJLT are reduced by 57%, 17% and 10% respectively over the existing SOIJLT device. The fabrication flow of the proposed Pi-OXJLT is proposed.
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