Low Power Design of Embedded SOC for TPM with Standard Library of 28 nm CMOS

Abstract

In the ultra-low nanometer semiconductor technology era, power consumption of integrated circuits should be considered as well as cell area and performance. Today, Clock Gating, Power Gating and Multi Voltage are the three most commonly used solutions in integrated circuits. However, single low power technique can not meet requirements of power savings in very high integration SOC (system on chip), especially from CMOS sub-28 nm technology on. Moreover, most of processors could only manage the power of the processors themselves, but could not manage the power of increasing user-integrated Ips (Intellectual Property cores). This paper proposed a power management unit, which has been integrated in low power design of an embedded SOC for TPM, to reduce the power consumption of the processor and user-integrated IPs. The design was implemented with CMOS 28 nm technology and fused Clock Gating, Power Gating and Multi Voltage techniques, achieving 86.08% total power savings and receiving 9.83% cell area penalty according to reports of synthesis tool.