Comparative Review of Approximate Multipliers

Abstract

In the digital signal processing (DSP) system, multiplier is a significant arithmetic module. It contributes mainly in the power consumption and speed, and efficient multipliers are the need of the hour. Approximate computing has added a unique dimension in the area of digital design by reducing area, power and delay. The demand of efficient approximate multipliers is enhancing due to the high speed and fault tolerance as well as its power efficiency. This paper presents comparison of few recent approximate multiplier designs. Experimental results based on the accuracy and circuit parameters are presented. The accuracy parameters are amplitude data accuracy (ACC_amp), information data accuracy (ACC_inf), error rate (ER) and mean error distance (MED). The circuit parameters are delay, power consumption, area. Based on these parameters, the best design in terms of power consumption and area is datapath complexity reduction approximate multiplier which exhibits 58% less power and 61% less area as compared to broken array multiplier.