Automated multi-device placement, I/O voltage supply assignment, and pin assignment in circuit board design

D. Seemuth, Katherine Morrow
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引用次数: 2

Abstract

Embedded systems often contain many components, some with multiple Field Programmable Gate Arrays (FPGAs). Designing Printed Circuit Boards (PCBs) for these systems can be a complex process that is often tedious, error-prone, and time-intensive. Existing computer-aided design tools require designers to manually insert components and explicitly define the connections between every component on the PCB - a cumbersome process. A fast PCB design framework requiring reduced designer time and effort would be particularly advantageous for rapid prototyping and short production run PCBs. Therefore, this paper proposes a novel, freely-available open-source framework to capture design intent and automatically implement the design details. Designers express connectivity at a higher level of abstraction than enumerating or drawing each individual trace between components. Given the components and connection requirements, the proposed framework automatically generates component placements, I/O voltage supply assignments, and FPGA pin assignments to minimize trace length. We also propose a novel method to improve trace length estimations during placement, before FPGA pins have actually been assigned to those connections. The proposed framework quickly explores large solution spaces, enabling rapid prototyping and design space exploration, and can lead to lower costs in design time and other non-recurring expenses. We demonstrate that it produces favorable results for various design requirements, which suggests the framework will be especially appreciated by designers of systems with multiple FPGAs having large numbers of flexible pins.
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电路板设计中的自动化多器件放置,I/O电压分配和引脚分配
嵌入式系统通常包含许多组件,其中一些包含多个现场可编程门阵列(fpga)。为这些系统设计印刷电路板(pcb)可能是一个复杂的过程,通常是乏味的,容易出错的,耗时的。现有的计算机辅助设计工具要求设计人员手动插入组件,并明确定义PCB上每个组件之间的连接,这是一个繁琐的过程。一个快速的PCB设计框架需要减少设计人员的时间和精力,这对于快速原型设计和短时间生产PCB尤其有利。因此,本文提出了一种新的、免费的开源框架来捕获设计意图并自动实现设计细节。设计人员在更高的抽象层次上表达连接性,而不是枚举或绘制组件之间的每个单独的轨迹。给定组件和连接要求,提议的框架自动生成组件位置、I/O电压供应分配和FPGA引脚分配,以最小化走线长度。我们还提出了一种新的方法来改进在FPGA引脚实际分配给这些连接之前放置期间的跟踪长度估计。所建议的框架可以快速探索大型解决方案空间,支持快速原型和设计空间探索,并且可以降低设计时间和其他非重复性费用的成本。我们证明了它对各种设计要求产生了有利的结果,这表明该框架将特别受到具有大量柔性引脚的多个fpga系统的设计者的赞赏。
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