{"title":"Improved Delta Sigma Analog to Digital Converter","authors":"A. Katara, S. Ramteke, A. Bapat, Swapnil Jain","doi":"10.1109/CICN.2011.93","DOIUrl":null,"url":null,"abstract":"This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time over sampling may be reduced or even eliminated. By doubling the number of Lth-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta- sigma modulators in parallel with no over sampling is similar to operating the same modulator with an over sampling rate of M. A parallel delta-sigma A/D converter implementation composed of two, four, and eight second-order delta-sigma modulators is described that does not require over sampling.","PeriodicalId":292190,"journal":{"name":"2011 International Conference on Computational Intelligence and Communication Networks","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 International Conference on Computational Intelligence and Communication Networks","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICN.2011.93","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time over sampling may be reduced or even eliminated. By doubling the number of Lth-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta- sigma modulators in parallel with no over sampling is similar to operating the same modulator with an over sampling rate of M. A parallel delta-sigma A/D converter implementation composed of two, four, and eight second-order delta-sigma modulators is described that does not require over sampling.