Layout design of on-chip transformer with uniform variation of coil widths

Abstract

A novel layout of variable width transformer is proposed to minimize the metal resistance in this study. Compared with reported paper [1], the sophisticated approach obtains a local minimum by equalizing the width ratio of primary and secondary coils. Two on-chip transformers with identical self inductance and chip area are fabricated to verify the proposed algorithm in CMOS technology. Measurement results demonstrate that the improvement of metal resistance approximates to the value of 10.36 %.