Estimation of the defective I/sub DDQ/ caused by shorts in deep-submicron CMOS ICs

Abstract

The defective I/sub DDQ/ in deep-submicron full complementary MOS circuits with shorts is estimated. High performance and also low power scenarios are considered. The technology scaling, including geometry reductions of the transistor dimensions, power supply voltage reduction, carrier mobility degradation and velocity saturation, is modeled. By means of the characterization of the saturation current of a simple MOSFET, a lower bound of I/sub DDQ/ defective consumption versus L/sub eff/ is found. Quiescent current consumption lower bound for shorts intragate, and shorts intergate affecting at least one logic node is evaluated. The methodology is used to estimate the I/sub DDQ/ distribution, for a given input vector, of defective circuits. This I/sub DDQ/ estimation allows the determination of the threshold value to be used for the faulty/fault-free circuit classification.