Computational complexity in logic testing

Abstract

The paper is concerned with analyzing and comparing two exact algorithms from the viewpoint of computational complexity. Both are for calculating fault-detection tests for digital circuits. The first one is the so-called composite justification, and the second is the D-algorithm. The analysis will be performed on combinational logic networks at the gate level. Here single and multiple stuck-at logic faults will be considered. As a result, it is pointed out that the composite justification requires significantly less computational step than the D-algorithm and its modifications. From this fact it has been concluded that possibly no other algorithm is available in this field with fewer computational steps. If it holds, then it follows directly that the test calculation problem is of exponential-time, and so are any other NP-complete problems.