Power efficient distributed low-noise amplifier in 90 nm CMOS

Brecht Machiels, P. Reynaert, M. Steyaert
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引用次数: 19

Abstract

A low-power wideband distributed low-noise amplifier (DLNA) in 90 nm CMOS is presented. Various techniques have been combined in the design to increase the distributed amplifier's power efficiency. These techniques range from moderate inversion biasing to transmission line tapering. The measured gain of the 12.5 mW DLNA is larger than 15 dB from DC to 21 GHz. The average noise figure in the pass-band is 5.4 dB, the IIP3 at 5 GHz is ࢤ6.6 dBm and the total die area is 0.41 mm2.
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90nm CMOS的高效功率分布式低噪声放大器
提出了一种90nm CMOS低功耗宽带分布式低噪声放大器。在设计中结合了多种技术来提高分布式放大器的功率效率。这些技术范围从适度的反转偏置到传输线变细。在直流至21 GHz范围内,12.5 mW DLNA的测量增益大于15 dB。通带内的平均噪声系数为5.4 dB, 5 GHz时的IIP3为ࢤ6.6 dBm,总芯片面积为0.41 mm2。
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