A Fast Approach for Deep Neural Network Implementation on FPGA

Abstract

Stochastic computing (SC) has received tremendous attentions for implementation of artificial neural networks (ANN). The hardware complexity of such an implementation is significantly reduced in comparison with conventional counterpart. One of major problems regarding the SC implementation of ANN is its slow convergence rate. Millions of clocks are required to generate a fairly accurate output by a single neuron. In this paper, a novel approach is developed in which the results of stochastic operations are determined after a specific clock cycle. The proper handshaking signaling are utilized among the interconnected neurons to interchange the necessary information. The proposed architecture is implemented on Virtex7 FPGA. The simulation results show a great improvement in accuracy along with significant speed up.