High Gain Low Offset Faster Two Stage CMOS Op-Amp and Effects of Aspect Ratios on Gain

Abstract

In this paper, a low voltage, low power, low offset and faster two stage CMOS operational amplifier exhibiting 60.24 dB dc gain and 51.1 MHz gain bandwidth with 61.6° phase margin, 8.4 mV offset voltage and 1.4 ns settling time using gpdk090 process is presented. Our designed Op-amp operates at ±1.8V supply voltage with 1.15 mW power dissipation. At first, various Op-amp specifications such as slew rate, gain bandwidth, ICMR, power dissipation are assumed and then optimized aspect ratios of MOSFETs are calculated based on these specified parameters and standard equations. Using CADENCE Virtuoso we have simulated our design and checked with our specifications. Moreover, the dependence of changing $\left(\frac {W}{L}\right)$ ratios of MOSFETs on gain to tune the gain at the time of designing Op-amp most effectively has also been investigated in this work. Finally, an analysis and simulations of high frequency square wave generation using this op-amp have been reported.