A 40 Gb/s PAM4 SerDes Receiver in 65nm CMOS Technology

Abstract

This paper presents a 40 Gb/s SerDes receiver for 4-level pulse-amplitude modulation (P AM4) data. After a voltage-shifting amplifier which works as a 3-level slicer, the input P AM4 signal is quantized into thermometer code, and then it is converted into two parallel binary signal by a decoder as the output. Also, an equalizer is designed to deal with the channel attenuation and a Clock and a 20 Gb/s full-rate Clock and Data Recovery (CDR) to recovery correct clock from input data. The whole circuit is designed in 65nm CMOS technology with an area of $1\times 0.7\ \mathbf{mm}^{2}$. Simulation results show that the eye opening of the output data is about 0.9UI and the jitter of the recovered clock is around 3.2 ps. Under 1.2V power supply, the power consumption is about 270mW.