{"title":"A 41-phase switched-capacitor power converter with 3.8mV output ripple and 81% efficiency in baseline 90nm CMOS","authors":"Gerard Villar Pique","doi":"10.1109/ISSCC.2012.6176892","DOIUrl":null,"url":null,"abstract":"This work presents a switched-capacitor power converter (SCPC) with a power density of 38.6mW/mm2 at 81% efficiency and 3.8mV output voltage ripple (ΔV0) in baseline 90nm CMOS. The design implements two different conversion ratios to maximize efficiency for a wide range of input voltages, and the use of 41 phases results in a very low output voltage ripple and low input current spikes.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"75 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"73","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE International Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2012.6176892","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 73
Abstract
This work presents a switched-capacitor power converter (SCPC) with a power density of 38.6mW/mm2 at 81% efficiency and 3.8mV output voltage ripple (ΔV0) in baseline 90nm CMOS. The design implements two different conversion ratios to maximize efficiency for a wide range of input voltages, and the use of 41 phases results in a very low output voltage ripple and low input current spikes.
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