Impact Analysis of Parasitic Capacitance of High-Insulation High-Frequency Transformer on Series Resonant Converter and Optimal Design

Abstract

The series resonant converter (SRC) is one of the most popular galvanically isolated dc–dc converters since it provides zero voltage switching (ZVS), reduces rms currents, using transformer leakage inductance as the resonant inductance can further reduce the volume of the converter. However, in medium-voltage (MV) grid to low-voltage (LV) DC bus applications, in order to meet the transformer's high insulation strength and high power requirements, the parasitic capacitance is large, causing resonance voltage and current oscillations spikes. The equivalent circuit is established, the mathematical expression of the resonant voltage and current in the time domain is established, and the adverse effects in the transient process are analyzed. The influence of different parasitic capacitance and dead time on oscillation is analyzed and compared, and design reference is given. Theoretical calculations is experimentally verified for the SiC MOSFET-based prototype of a 2kV DC input, 800V output, 10kVDC insulation, 4kW power output, which operates at 200kHz, with an efficiency of 98.5%. Experimental comparison shows that the proposed method reduces the voltage and current oscillation disappeared spikes from 1.3 times the steady-state value.