High Speed and Low Power Comparator in 65 nm CMOS for Energy Efficient Biomedical SAR ADCs

Abstract

Complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) have recently focused on smaller size, lower supply voltage, and power consumption, contributing to the development of power and noise efficient biomedical devices. Since the nature of the biomedical signal is analog, power efficient analog to digital converter (ADC) is needed to translate these signals from physical to digital domain for further processing. This conversion process requires a comparator circuit which becomes the core of energy efficient ADCs. However, the speed and power consumption represent challenges for such designs. This paper presents a CMOS high speed, and low power comparator design used for successive approximation registerSAR ADCs. The proposed design is simulated and analyzed using 65 nm CMOS process. Simulation results for the proposed comparator show that the circuit consumes 70 μ w at 5 GHz of sampling clock with 1V supply. The implications of these results and how critical can the circuit parameters limit the dynamic performance of the comparator circuit are discussed.