A systolic array for fault tolerant digital signal processing using a residue number system approach

Abstract

Fault detection and correction using the Chinese remainder theorem for decoding is investigated. It is shown that this approach is well suited for implementation by VLSI circuits for digital signal processing using systolic architectures. A systolic array for multioperand residue addition is considered, and its application in error-tolerant digital signal processing is presented. It is shown that the array can be easily used for comparing efficiently a set of residues S=(x/sub 0/, x/sub 1/, . . ., x/sub N-1/) to a known constant. This algorithm has been used to detect errors by checking whether S lies in the illegitimate range. The multioperand residue adder has been modified to design a variable modulus adder. An error-tolerant RNS finite-impulse response filter has been designed using this variable modulus adder. Three schemes for error detection and correction are proposed.<>