Delay and Energy Efficient Design of On-Chip Encoded Bus with Repeaters

Abstract

In this paper, we propose a new spatial and temporal encoding approach for generic on-chip global buses with repeaters that enables higher performance while reducing peak energy and average energy. The proposed encoding approach exploits the benefits of temporal encoding circuit and spatial bus-invert coding techniques to simultaneously eliminate opposite transitions on adjacent wires and reduce the number of self-transitions and coupling-transitions. In the design process of applying encoding techniques for reduced bus delay and energy, we present a repeater insertion design methodology to determine the repeater size and inter-repeater bus length which minimizes the total bus energy dissipation while satisfying target delay and slew-rate constraints. This methodology can be employed to obtain optimal energy vs. delay trade-offs under slew-rate constraint for various encoding techniques.