A configurable, programmable and software-defined network on chip

Abstract

The rapidly developing multi-cores integration on a chip requires efficient networking. To catch up the evolvement of on-chip network technologies and reduce the cost of redesign and redeployment, the software-defined solution is required on chip instead of proprietary design and straightforward replacement of hardware. In this paper, we propose the software defined on-chip network (SDNoC), which is a configurable and programmable network on chip with the idea of software defined networking. SDNoC separates on-chip network into the control plane and data forwarding plane, so that control logic is decoupled from the underlying chip hardware, and applications are able to configure the network according to their requirements. The simulation evaluates the SDNoC compared with the static and dynamic routing schemes in the traditional on-chip network, and shows SDNoC is able to improve the network performance and reduce power consumption with the programmable control logic and application-specific configuration.