Power Efficient FPGA-based TCAM Architecture by using Segmented Matchline Strategy

Abstract

Ternary content-addressable memory (TCAM) is famous for its high-speed search operation but this speed comes at the cost of high-power consumption. The paper presents a power efficient architecture for TCAM on field-programmable gate array (FPGA) by using segmented matchline (ML) strategy. Each ML is divided into four equal segments where each segment has nine bits. The proposed TCAM architecture is implemented on Xilinx Virtex-6 FPGA for the size of $64\times 36$. Implementation results show that during search operation, the proposed TCAM results in 13.88% reduction in dynamic power consumption compared to the latest FPGA-based TCAMs while not compromising on speed.