Development of low-power high speed (10Gb/s) drivers in CMOS 130 nm technology

Abstract

The aim of this work is to develop a dedicated low power transmitter interface for high-speed data transmission in CMOS 130 nm technology. Such interface is necessary in complex ASICs working at high frequencies and processing large amounts of data, in particular it is needed in advanced detector readout systems of particle physics experiments. New multichannel readout ASICs, capable to transmit data at high frequencies (>5Gb/s), with low jitter, and consuming very low power, are recently being intensively developed. A Current Mode Logic (CML) and Source-Series Terminated (SST) interfaces are natural candidates to drive the data out of the chip. A broadband extension techniques using inductors may be applied to extend the bandwidth of these drivers. Unfortunataly, inductors occupy very large area what limits their applications in ASICs. In this work the CML driver using inductive peaking and two SST drivers (with, without series peaking) were developed to achieve transmission speeds between 5-10 Gb/s, together with very low (<;2 ps) jittter. We present and compare the schematic and post-layout simulations of the developed drivers together with all relevant parameters (speed, jitter, eye diagram). Prototype designs in CMOS 130 nm were already submitted and are now in fabrication.