Tang-Nian Luo, Shuen-Yin Bai, Y. Chen, Chun-Lin Ko, Chin-Fong Chiu, Y. Juang
{"title":"A 43 GHz 0.13μm CMOS prescaler","authors":"Tang-Nian Luo, Shuen-Yin Bai, Y. Chen, Chun-Lin Ko, Chin-Fong Chiu, Y. Juang","doi":"10.1109/RWS.2008.4463458","DOIUrl":null,"url":null,"abstract":"This paper presents a 43 GHz divide-by-three prescaler implemented in 0.13 mum CMOS technology. The variation of regenerative topology is used to perform frequency division by three at millimeter-wave frequency. The band-pass filtering is developed with circuit parasitics to suppress unwanted harmonics. By combining the Gilbert-cell mixer and differential injection locked oscillator, the maximum operating frequency of the CMOS divide-by-three prescaler is elevated to 43 GHz. The measured phase noise is -108.8 dBc/Hz at 1 MHz offset from the output signal frequency. Operated at 2 V, the prescaler consumes 16 mW of power. The total chip size is 0.8times0.6 mm2.","PeriodicalId":431471,"journal":{"name":"2008 IEEE Radio and Wireless Symposium","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Radio and Wireless Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RWS.2008.4463458","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
This paper presents a 43 GHz divide-by-three prescaler implemented in 0.13 mum CMOS technology. The variation of regenerative topology is used to perform frequency division by three at millimeter-wave frequency. The band-pass filtering is developed with circuit parasitics to suppress unwanted harmonics. By combining the Gilbert-cell mixer and differential injection locked oscillator, the maximum operating frequency of the CMOS divide-by-three prescaler is elevated to 43 GHz. The measured phase noise is -108.8 dBc/Hz at 1 MHz offset from the output signal frequency. Operated at 2 V, the prescaler consumes 16 mW of power. The total chip size is 0.8times0.6 mm2.