A 43 GHz 0.13μm CMOS prescaler

Tang-Nian Luo, Shuen-Yin Bai, Y. Chen, Chun-Lin Ko, Chin-Fong Chiu, Y. Juang
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引用次数: 4

Abstract

This paper presents a 43 GHz divide-by-three prescaler implemented in 0.13 mum CMOS technology. The variation of regenerative topology is used to perform frequency division by three at millimeter-wave frequency. The band-pass filtering is developed with circuit parasitics to suppress unwanted harmonics. By combining the Gilbert-cell mixer and differential injection locked oscillator, the maximum operating frequency of the CMOS divide-by-three prescaler is elevated to 43 GHz. The measured phase noise is -108.8 dBc/Hz at 1 MHz offset from the output signal frequency. Operated at 2 V, the prescaler consumes 16 mW of power. The total chip size is 0.8times0.6 mm2.
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43 GHz 0.13μm CMOS预分频器
本文提出了一种采用0.13 μ m CMOS技术实现的43 GHz / 3预分频器。利用再生拓扑的变化在毫米波频率上实现三分频。采用电路寄生的带通滤波方法抑制不必要的谐波。通过结合Gilbert-cell混频器和差分注入锁定振荡器,CMOS除以3预分频器的最大工作频率提升到43 GHz。测量的相位噪声为-108.8 dBc/Hz,与输出信号频率偏移1mhz。在2v电压下工作,预分频器消耗16mw的功率。芯片总尺寸为0.8 × 0.6 mm2。
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