Method to Generate Bus Stress Pattern Using iBUS(Infineon Bus Under Stress) framework

Abstract

Infineon BUS Under Stress (iBUS) framework generates test scenarios for stressing various system buses and bridges inside a microcontroller. Randomization is the key approach behind iBUS. The framework is designed to be scalable, platform independent and forward compatible. Buses and Bridges enters into active state when the bus masters try to access the memories for transferring the data. A test scenario generated by iBUS enables all the BUS masters to perform parallel data transfers between various memories of the system in a purely randomized way. This framework ensures that there is no overlap of memories when accessed by different masters and also provides self-checking mechanism to verify data integrity. In this paper, we characterize the flexibility of iBUS as it can design task chains (sequences of memories handled by a master), calculation of randomized payload and assign random data lengths (based on memory type) in a single block transfer. This paper will also provide insight into how randomization will widen the range of the test coverage. As many are the tasks (transfer between a source and destination memory), that many are the possible combinations of bridges accessed inside the test. Framework provides various hooks to debug the failures and could be used in Robustness Validation, Power Cycling, Clock Shmoo and other silicon stress conditions.