An oxide failure reliability model for shallow trench isolation based LDMOS devices

Abstract

Using an intrinsic percolation model, this paper presents a statistical model which predicts the probability of Shallow Trench Isolation (STI) breakdown as a result of aging in N-type Laterally Diffused MOSFET (NLDMOS). During the STI's etch process particles might “shadow” the silicon etch resulting in protrusions of Si at different depths and locations. This effect which normally has a negligible effect on device long term failure may become pronounced for large NLDMOS switches. The model allows to define common stress tests needed to invoke failure, and hence the removal, of devices with critical defects. The failure probability with time for the remaining devices is calculated. A numerical example is presented in the last section.