A novel parallel adaptation of an implicit path delay grading method

Abstract

For large modern circuits, it is desirable to trade hardware cost for time when making path delay fault coverage estimates, especially as a subroutine for ATPG and timing analysis solutions. A parallel adaptation of an established framework for implicit path delay fault grading on with a GPGPU implementation is presented. Experimental evaluation on a NVIDIA Tesla C2075 GPU shows on average 50x speedup against the basic version for the framework on an Intel Xeon E5504 host system. Over a 1200x speedup is observed against a single-threaded, more complex version in the framework which grades more faults.