Countermeasures Against Information Leakage Induced by Data Serialization Effects in a RISC CPU

Abstract

Side-channel attacks (SCAs) utilize the side-channel information leakage of devices to obtain sensitive information, which have become one of the most prominent threats to the security of embedded systems. Information leakage induced by data serialization effects is a critical problem in designing countermeasures against SCAs. In this paper, information leakage induced by data serialization effects in a general-purpose RISC CPU with a three-stage pipeline is studied. The side-channel analysis is based on the netlist-level simulation to guarantee a "clean room" environment. Based on the implementation of SCAs by using correlation power analysis (CPA) method, information leakage is significant in the CPU and the correct key is successfully guessed with the help of only tens of power traces. Three countermeasures based on software and hardware are proposed and compared with consideration of CPU security, performance and power consumption. After implementing the countermeasures, the information leakage is reduced significantly and the anti-attack ability of the CPU is improved (up to four orders of magnitude). Moreover, when the countermeasures are implemented in actual noisy environment, the CPU security will be further improved. Reasonable compromise needs to be made between the CPU security and implementation overhead to choose suitable SCA-resistant countermeasures under different conditions.