A Novel Reconfigurable Architecture for Temporal and Spatial Application Mapping

Abstract

This paper introduces a novel FPGA-like architecture that can perform operations in space (for maximum performance) or in time (for minimum hardware area) at logic-cell level. Based on our previous work concerning DSP applications mapping onto ASTRA reconfigurable architecture, this paper describes the microarchitecture in more detail and introduces some significant improvements. The silicon area of the logic tile is reduced by 40%. The area figures of the benchmarks are only factor 10-25 worse than the ASIC implementation - a very competitive ratio for a reconfigurable architecture.