Formal Modelling and Verification of Spinlocks at Instruction Level

Abstract

Spinlocks have been widely used as a solution for synchronous accesses to shared resources, and their correctness is critical to guarantee the consistency of concurrent processes. This paper presents formal models and machine-checked verification of the correctness of spinlocks at instruction level. We present the formal verification of two spinlocks, which are spinlocks implemented based on the ARM instructions and the x86 instructions, respectively. Our model formalizes the lowlevel instructions that are necessary to capture the execution of spinlocks, characterizes the processor hardware mechanisms related to each instruction, and considers the context switches on processors and two-level scheduling of processors and processes. We specify the correctness property of our models, that is, accesses of a critical section satisfy mutual exclusion, and verify that the models satisfy the property using the theorem prover Isabelle/HOL. With the verification experience, we give some suggestions on how to implement spinlock leveraging the ARM ISA.