Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process

Abstract

Electrostatic discharge (ESD) is an inevitable event in CMOS integrated circuits. Layout structure is one of the important factors that affect ESD robustness of MOS transistors. In this work, the impact of inserting additional layout pickups to ESD robustness of both multi-finger NMOS and PMOS transistors has been studied in a 90-nm CMOS process. Measurement results have shown that multi-finger MOS transistors without additional pickup inserted into their source regions can sustain a higher ESD protection level at the same effective device dimension.