Imperfectly connected 2D arrays for image processing

Abstract

An image processing architecture designed for ultralarge-scale and wafer-scale integration which uses a novel fault-tolerance strategy is described. The strategy overcomes many of the problems associated with configuring a 2D array from cells and spares with some kind of switching network. It provides a novel approach to fault tolerance because the primary mechanism for tolerating faults is neither hardware redundancy nor time redundancy but is a trade against processing resolution. The architecture provides a working, gracefully degrading array for image processing.<>