Digital filter ASIC for NASA deep space radio science receiver

Proceedings of Eighth International Application Specific Integrated Circuits Conference Pub Date : 1995-03-01 DOI:10.1109/ASIC.1995.580677

J. Kowalski, J. Berner

引用次数: 1

Abstract

Implementation of an 80 MHz, 16-bit, multi-stage digital filter to decimate by 1600, providing a 50 kHz output with bandpass ripple of less than +/-0.1 dB is described. It uses two decimation by five units and six decimations by two executed by a single decimation by two unit. The six decimations by two consist of six halfband filters, five having 19-taps and one having 51-taps. Use of 16/spl times/16 register files for the digital delay lines and programmable coefficients enables implementation in the Vitesse 350 K gate array.

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NASA深空无线电科学接收机数字滤波专用集成电路

实现一个80 MHz, 16位，多级数字滤波器，抽取1600，提供50 kHz输出，带通纹波小于+/-0.1 dB。它使用2次5个单位的抽取和6次2个单位的抽取，由一次2个单位的抽取执行。六次抽取由六个半带滤波器组成，五个有19个抽头，一个有51个抽头。对于数字延迟线和可编程系数，使用16/spl times/16寄存器文件可以在Vitesse 350k门阵列中实现。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of Eighth International Application Specific Integrated Circuits Conference

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